Verilog-AMS
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Verilog-AMS是Verilog硬體描述語言的一個衍生。它包含了類比和混訊擴展模塊,以實現對於類比電路和混訊系統行為的描述。它擴展了Verilog、SystemVerilog等的事件驅動仿真器的迴路,通過使用一個連續時間仿真器,可以在類比域(analog-domain)上求解微分方程。類比事件可以觸發數位行為,反之亦可。[1]
參考文獻
- ^ Scheduling semantics are specified in the Verilog/AMS Language Reference Manual, section 8.
外部連結
- I. Miller and T. Cassagnes, "Verilog-AMS Eases Mixed Mode Signal Simulation," Technical Proceedings of the 2000 International Conference on Modeling and Simulation of Microsystems, pp. 305-308, Available: https://web.archive.org/web/20070927051749/http://www.nsti.org/publ/MSM2000/T31.01.pdf
一般的資料
- Accellera Verilog Analog Mixed-Signal Group
- verilog-ams.com
- The Designer's Guide Community, Verilog-A/MS (頁面存檔備份,存於網際網路檔案館) — Examples of models written in Verilog-AMS]
- EDA.ORG AMS Wiki(頁面存檔備份,存於網際網路檔案館) - Issues, future development, SystemVerilog integration
開源資料
- OpenVAMS, a Open-Source VerilogAMS-1.3 Parser with internal VPI-like representation (頁面存檔備份,存於網際網路檔案館)
- V2000 project - Verilog-AMS parser & elaborator (頁面存檔備份,存於網際網路檔案館)
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